Today, many fabless chip design companies are actively evaluating the suitability of 5nm process technology for their upcoming SoC designs. If you’re an engineering executive tasked to weigh the risks and rewards of moving your company’s next flagship product to 5nm, how prepared are you to make this decision? This is a complex choice, hinging on whether the business benefits of 5nm outweigh the engineering challenges. This post guides you through answering three critical questions about your goals, design, target applications, tools and choice of foundry to help you make the best decision for your company.

1. What are the advantages of implementing my SoC in 5nm versus previous nodes, and will these advantages benefit my target applications and use case?

According to Moore’s Law, with greater transistor density comes more processing capacity in a smaller space with better power efficiency, and so it will be for 5nm. Sounds like a no-brainer for your new SoC, but remember 5nm is still an emerging technology, not yet supported by mature, high-yield processes. So, it’s important to ensure your design and the applications it targets will benefit from these efficiencies.

For example, high-performance computing and low-power mobile designs are two examples of end markets well suited to 5nm because best-in-class performance and power efficiency offer significant competitive advantages. To benefit from the power, performance, or area (PPA) advantages of 5nm, your SoC features or design goals should include at least one of the following. The need to:

• integrate more functionality than the previous generation or design, such as additional memory, multiple processor cores or new high-speed interfaces, without a significant change in PPA.

• fit more functionality in one package than previous generations or designs. Alternatively, your design might be better suited to chiplets in a system-in-package.

• address power consumption or power density issues for battery-operated devices that you couldn’t solve efficiently in a legacy process.

• provide specific process tuning for your application domain such as automotive (e.g., functional safety considerations, ISO 26262/ASIL-D qualification) or data center (high performance, high bandwidth) that wasn’t possible in a legacy process.

Thinking through these requirements will give you a deeper and prioritized understanding of the specific advantages that 5nm processes could bring to your design, end application or target market that cannot be easily achieved in a mature process, such as 7nm or 10nm.

2. What challenges should I anticipate when implementing my SoC in 5nm versus previous nodes?

As you research the 5 nm process at a particular foundry, you’ll face many design, implementation and verification challenges. Even after receiving a new 5nm PDK, you should expect architectural, logic and physical design challenges, all of which should factor into the 5nm go/no-go decision. Here are a few of the major differences to anticipate between 5nm and previous nodes.

• Investment in a test chip is no longer optional. Migration of existing internal design and external IP to a new process is a perennial challenge with each new node. However, it becomes mission-critical for 5nm as the risk of not proving the IP with a test chip beforehand can be catastrophic. The more tuned your design is to the previous process, and the older the process (i.e., non-FinFET/planar), the more challenging it will be to migrate to 5nm. Even some “production-proven” IPs such as GPIO and DDRs will have to be reworked.

In 5nm, test chips are the only way to uncover the full extent of migration challenges. They will reveal the DRC and LVS issues you were unaware of in your design or the previous process. Also, make sure you select the right IPs for a test chip, as you will learn a lot about yield based on the IPs you choose. Standard yield numbers based on SRAMs and specific processor cores may not be representative of your entire design, so pick some IPs that are a good mix of memory and logic, and some that are pushing the limits on performance or challenging design rules.

Don’t think your design is complex enough for a test chip? Then ask yourself: Why do I want to migrate to 5nm? Given the inevitable implementation challenges, it might make more sense to stay with proven nodes, such as 10nm or 16nm.

• Design technology co-optimization (DTCO) is now required. DTCO has existed for a long time as a well-known method of helping semiconductor fabs reduce cost and time-to-market in advanced process development. But with the move to smaller, more complex process nodes and the manufacturing of chip designs primarily in foundries, the need for a structured relationship for co-optimization has become essential.

DTCO enables highly accurate modeling and analysis of performance and power. It is mission critical when working in 5nm to address variable margins in process, wires and vias. In the 5nm process, the once relatively small margins between “ideal” and “actual” can now have a much more significant impact on chip performance, the tradeoff between power and heat, and other factors. Better modeling and accurate analysis provided by tools integrated into DTCO flows are a must if you are migrating to improve performance (i.e., higher frequency and multiple clocks) or lower power consumption (i.e., more power domains, complex power distribution, complicated power management units). Also, statistical timing models are now a necessity. Past approaches of closure at three process, voltage and temperature (PVT) corners will not be sufficient. How about ten corners? Maybe. Yes, it is time to get familiar with the signoff checklist again!

DTCO support varies across the EDA toolsets from industry leaders, but tools are not typically interoperable across vendors. Ensuring you have a complete toolset with comprehensive DTCO support may require an audit of and upgrade to your current EDA tools. I’ll discuss this issue further in an upcoming post.

• New rules for design for X (DfX). With 5nm comes some new design rules, so it’s essential to understand how they might impact your designs. A thorough list isn’t practical here, so I’ll share a few typical examples.

° Custom sizing options for transistors are gone in 5nm; all geometries are uniform height and width. This means there are fewer design rules, about 50 instead of 400!

° There are new design for manufacturability (DfM) rules, and some of the older rules, such as coloring cells, are changing. Markers are now every 100 microns instead of 1,000 microns.

° Design for reliability (DfR) requires the addition of power surge protection circuits.

If you’ve migrated one or more designs to a new process in the past, you may have dealt with some of these issues before. However, the scale and complexity of these problems are greater as you move to 5nm, especially if your last design was not on FinFET (16nm or smaller), or if it didn’t stress PPA issues significantly.

3. What challenges should I anticipate when implementing my SoC in 5nm versus previous nodes?

Not everyone on your engineering team needs to be an expert in the 5nm manufacturing process. The most significant impact will be on the physical designers, chip finishing engineers and test engineers. Many, if not all, will need to understand the true extent of DfX impact, which includes DfM and DfR, plus design for debug, design for test, design for yield, and now, design for inspection. Timing engineers will need to update their skills regarding the accuracy of model, mode and configuration settings in their analysis tools and the interpretation of the results. Even for front-end designers and verification engineers, dealing with the increased design complexity will require changing or enhancing the design data repository and introducing additional rules in their linting tools.